1. Technical Field
The present invention relates generally to an improved method for frequency generation and in particular to an apparatus and a method for adjusting the generated frequency. Still more particularly, the present invention provides an apparatus and a method for high resolution frequency adjustment using a multistage frequency synthesized.
2. Description of the Related Art
A phase locked loop (PLL) is a very interesting integrated circuit that blends analog and digital techniques. Although the basic design of a PLL has been known for decades, the circuit only became a practical building block in integrated circuit form where the cost has become affordable and the design has become more reliable.
The PLL contains a phase detector, an amplifier, a voltage controlled oscillator (VCO), and a feedback loop that allows the output frequency to be a replication of the input signal with noise removed or a multiple of the frequency of the input signal. PLLs have been used for demodulation of FM signals, for tone decoding, for frequency generation, for generation of xe2x80x9ccleanxe2x80x9d signals, and for pulse synchronization, to name but a few of the applications. Because the output frequency is a multiple of the input frequency, it is difficult to make fine frequency adjustments using such a frequency synthesizer.
A non-uniform memory access (NUMA) computer system is a multiple processor architecture where there is a single memory address space but where memory is separated into xe2x80x9cclosexe2x80x9d banks of memory and xe2x80x9cdistantxe2x80x9d banks of memory. Access is xe2x80x9cnon-uniformxe2x80x9d because the access times for the close banks of memory directly associated with the node that contains the CPU are much faster than the access times for distant memory banks at other nodes in the system. A distinct advantage of a NUMA architecture is that it scales well, in the sense that adding more nodes and processors to the system does not create bottlenecks that degrade performance in the same way as other parallel architectures.
One problem with NUMA architectures is to keep the nodes synchronized. Transactions are often labeled with time stamps that are generated by the time of day at each node in the system. Since these nodes have independent clocks, even though they are initialized at precisely the same time, they will eventually drift apart and require re-synchronization. It is important to have precise time stamps with as little xe2x80x9ccycle slippagexe2x80x9d as possible between the nodes.
Therefore, it would be advantageous to have a frequency synthesizer that is capable of rapid, high resolution frequency adjustments.
An apparatus and a method is presented for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider.
There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider.
By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.